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Author Topic: Boot block address 2x parallel-rom (was Too lazy to disassemble or find out)  (Read 3738 times)

stepleton

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The Lisas are all the way over in the other room, and I'd have to write a program or mess around with Service Mode anyway (and so same for LisaEm too). Maybe one of you just knows off the top of your head:

We know that the Lisa boot ROM loads the boot block data for a ProFile on the internal port to $20000. I think that the parallel port ROM puts it somewhere else --- the boot ROM loads the parallel port ROM at $20000 or so, and then that ROM loads the boot block data... to a different place. I think that's what happens?

Does anyone know off the top of their head if that's right, and if so, what that address is?
« Last Edit: November 25, 2020, 06:34:15 am by rayarachelian »
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rayarachelian

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Re: Too lazy to disassemble or find out :-)
« Reply #1 on: November 24, 2020, 09:27:24 pm »

Sounds like a job for... (drum roll) tracelog!

I setup a test case for this by setting all 3 slots to the dual parallel card and set both ports to profiles and booted off #9, though D0 was loaded with #$0a on the boot routine.

So interestingly it's smart enough to load the expansion slot ROM only once. I was under the impression that it would load the code for all the slots at 20000.
Possibly it loads the parallel rom code first when it tests the codes and get icons, and again when a boot device is selected, not sure, didn't dig that deep, but might be interesting to tweak the card ID value and stick in 3 slightly different ROMs to see if all 3 are loaded and see what happens then.

Also seems that the health check routine for the dual parallel does nothing to other than clear D0 and RTS. It should be doing some kind of self-check/test.

On boot, the device number is passed in D0 when the boot routine is called which then compares this to various values and then makes some decisions around this. Perhaps these matter somehow to the address, not sure.

Eventually this is the IRA MOVE.L which reads the 4 status bytes. So this will eventually read the boot block into 20800 starting with the tags first.


 9141130 1/000203f8 (0 0/0/0) : 47f8 01b4                  : G...     :  780 : LEA.L      $000001b4,A3  SRC:clk:0000000025e09361 +8 clks
 9141131 D 0:00000000 1:00000000 2:00000002 3:0000000a 4:00000003 5:00000073 6:00000010 7:30000000 .Sz.... imsk:7 pnd:3 (0/0/normal cx:1)SRC:
 9141132 A 0:00fca801 1:000207fc 2:00020810 3:000001b4 4:00fe314a 5:00fe0742 6:001db3be 7:00000446 SP:00000000 PC:000203fc SRC:
 9141133
 9141134 1/000203fc (0 0/0/0) : 16e8 0008                  : ....     :  265 : MOVE.B     $0008(A0),(A3)+  SRC:clk:0000000025e09369 +16 clks
 9141135 src/lisa/cpu_board/memory.c:lisa_rb_io:3520:@00fca809| 21:00:39.6 635474793
 9141136 src/lisa/cpu_board/memory.c:lisa_rb_2x_parallel_h:1149:Access to lower VIA #7 at 00fca809 slot| 21:00:39.6 635474793
 9141137 src/lisa/io_board/via6522.c:lisa_rb_ext_2par_via:2212:VIA:7 reading from register 1 (I/ORA    )| 21:00:39.6 635474793
 9141138 src/storage/profile.c:ProfileLoop:727:----------------------------------------------------------------------| 21:00:39.6 635474793
...
 9141185 src/storage/profile.c:ProfileLoop:734:------------ State:10 PC:1/000203fc------------------------------------| 21:00:39.6 635474793
 9141186 src/storage/profile.c:ProfileLoop:1271:State:10, allow Lisa to read the status and data  - pointer:0| 21:00:39.6 635474793
 9141187 src/storage/profile.c:ProfileLoop:1295:Returning 00 from index:0| 21:00:39.6 635474793
 9141188 src/lisa/io_board/via6522.c:viaX_ira:1982:VIA:7 profile.c:READ 00 from ProFile, pc24:000203fc  tag:profile state:10| 21:00:39.6 635474793
 9141189 src/lisa/io_board/via6522.c:lisa_rb_ext_2par_via:2289:profile.c:widget.c: Profile->Lisa IRA2 00   pc24:000203fc| 21:00:39.6 635474793
 9141190 src/lisa/cpu_board/memory.c:dmem68k_fetch_byte:408::::::READ BYTE 00 ' ' from @1/00fca809 (phys @0000a809) using 24-io| 21:00:39.6 635474793
 9141191 src/lisa/cpu_board/memory.c:dmem68k_store_byte:486::::::WRITE BYTE 00 ' ' to @1/000001b4 using 17-ram| 21:00:39.6 635474793
 9141192 D 0:00000000 1:00000000 2:00000002 3:0000000a 4:00000003 5:00000073 6:00000010 7:30000000 .Sz.... imsk:7 pnd:3 (0/0/normal cx:1)SRC:
 9141193 A 0:00fca801 1:000207fc 2:00020810 3:000001b5 4:00fe314a 5:00fe0742 6:001db3be 7:00000446 SP:00000000 PC:00020400 SRC:
 9141194

Eventually we get here:
 9176517 1/000202f6 (0 0/0/0) : 3029 0004                  : 0...     :  467 : MOVE.W     $0004(A1),D0  SRC:clk:0000000025e0bb2f +12 clks
 9176518 src/lisa/cpu_board/memory.c:dmem68k_fetch_word:433::::::READ WORD aaaa '**' from @1/00020800 (phys @00020800) using 17-ram| 21:00:39.7 635484975
 9176519 D 0:0000aaaa 1:00000000 2:00090000 3:0000000a 4:00000003 5:00000073 6:00000010 7:30000000 .S..... imsk:7 pnd:3 (0/0/normal cx:1)SRC:
 9176520 A 0:00fca801 1:000207fc 2:00020810 3:00fe2194 4:00fe314a 5:00fe0742 6:001db3be 7:00000480 SP:00000000 PC:000202fa SRC:
 9176521
 9176522 cpu68k.c:cpu68k_ipc:613:dt_ImmW @ 000202fc target:0000aaaa opcode:0c40| 21:00:39.7 635484987
 9176523 1/000202fa (0 0/0/0) : 0c40 aaaa                  : ....     :  168 : CMP.W      #$aaaa,D0  SRC:clk:0000000025e0bb3b +8 clks
 9176524 D 0:0000aaaa 1:00000000 2:00090000 3:0000000a 4:00000003 5:00000073 6:00000010 7:30000000 .Sz.... imsk:7 pnd:3 (0/0/normal cx:1)SRC:
 9176525 A 0:00fca801 1:000207fc 2:00020810 3:00fe2194 4:00fe314a 5:00fe0742 6:001db3be 7:00000480 SP:00000000 PC:000202fe SRC:
 9176526
 9176527 1/000202fe (0 0/0/0) : 6742                       : gB       : 1054 : BEQ.B      $00020342  SRC:clk:0000000025e0bb43 +8 clks
 9176528 D 0:0000aaaa 1:00000000 2:00090000 3:0000000a 4:00000003 5:00000073 6:00000010 7:30000000 .Sz.... imsk:7 pnd:3 (0/0/normal cx:1)SRC:
 9176529 A 0:00fca801 1:000207fc 2:00020810 3:00fe2194 4:00fe314a 5:00fe0742 6:001db3be 7:00000480 SP:00000000 PC:00020342 SRC:
 9176530
 9176531 1/00020342 (0 0/0/0) : 4e92                       : N.       :  752 : JSR.L      (A2)  SRC:clk:0000000025e0bb4d +16 clks
 9176532 src/lisa/cpu_board/memory.c:dmem68k_store_long:533::::::WRITE LONG 00020344 ' CDD' to @1/0000047c  (phys @0000047c) using 17-ram| 21:00:39.7 635485005
 9176533 D 0:0000aaaa 1:00000000 2:00090000 3:0000000a 4:00000003 5:00000073 6:00000010 7:30000000 .Sz.... imsk:7 pnd:3 (0/0/normal cx:1)SRC:
 9176534 A 0:00fca801 1:000207fc 2:00020810 3:00fe2194 4:00fe314a 5:00fe0742 6:001db3be 7:0000047c SP:00000000 PC:00020810 SRC:
 9176535
 9176536 cpu68k.c:cpu68k_ipc:567:dt_Pdis @ 00020812 target:00020828 opcode:4efa| 21:00:39.7 635485021
 9176537 cpu68k.c:cpu68k_ipc:567:dt_Pdis @ 00020812 target:00020828 opcode:4efa| 21:00:39.7 635485021
 9176538 1/00020810 (0 0/0/0) : 4efa 0016                  : N...     :  764 : JMP.L      {PDIS:00020828}=(PC+#$0018) src:00020828 dst:00000036  SRC:clk:0000000025e0bb5d +10 clks
 9176539 D 0:0000aaaa 1:00000000 2:00090000 3:0000000a 4:00000003 5:00000073 6:00000010 7:30000000 .Sz.... imsk:7 pnd:3 (0/0/normal cx:1)SRC:
 9176540 A 0:00fca801 1:000207fc 2:00020810 3:00fe2194 4:00fe314a 5:00fe0742 6:001db3be 7:0000047c SP:00000000 PC:00020828 SRC:
 

So that's the starting address: 0x00020810. (edited)

However, if you're writing a new boot block/loader, I'd highly recommend using position independent code. i.e. Use LEA/PEA and PC offset JMP/JSR or BSR/BRA instead of using fixed addresses.

Also renaming the topic so when someone in the future searches "boot block address" they'll find this topic.
« Last Edit: November 25, 2020, 05:35:15 pm by rayarachelian »
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stepleton

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Brilliant, thanks very much, Ray!

Looking at your traces (and thanks also for not omitting those!) I wonder if there might be some minor corrections. I'm inclined to think that the boot block is loaded tags-first to $207FC: my reasons for this guess are
  • A1 takes this value in the traces
  • The code looks for the "bootable" marker $AAAA as $4(A1) or $20780 --- that tracks, since the "boot file id" is supposed to live four bytes into the tags
  • A2 holds $20810, which is $207FC+20, and ProFile tags are 20 bytes. There is a JSR to there just before the end of the trace
I'm guessing that the JMP $18(PC) is from the boot block and not from the boot ROM. If I'm right, it's mildly interesting that the parallel port card will JSR into the boot block while the boot ROM JMPs (line $1C96 here). The AppleNet card also seems to prefer a JSR.

Quote
However, if you're writing a new boot block/loader, I'd highly recommend using position independent code. i.e. Use LEA/PEA and PC offset JMP/JSR or BSR/BRA instead of using fixed addresses.

Oh, no worries there, bootloader_hd is completely relocatable. I can't guarantee that someone else's code is, though, so I want to replicate the parallel port card's behaviour closely :)
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rayarachelian

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Looking at your traces (and thanks also for not omitting those!) I wonder if there might be some minor corrections. I'm inclined to think that the boot block is loaded tags-first to $207FC: my reasons for this guess are
  • A1 takes this value in the traces
  • The code looks for the "bootable" marker $AAAA as $4(A1) or $20780 --- that tracks, since the "boot file id" is supposed to live four bytes into the tags
  • A2 holds $20810, which is $207FC+20, and ProFile tags are 20 bytes. There is a JSR to there just before the end of the trace

Right you are, edited to fix that. Let me know if you want the tracelog, it's about 8MB compressed w/lz something like 100MB uncompressed I'd guess.
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