General Category > LisaList2
Cameo/Aphid selector
rayarachelian:
--- Quote from: stepleton on January 20, 2021, 05:49:38 pm ---That's what I'd hoped at first too. Unfortunately the problem shows up on both of the parallel cards that I own, and both cards' upper ports work fine with a real ProFile or with an IDEfile.
--- End quote ---
Hmm, so this would imply there's something different about the ports. Been looking at http://bitsavers.org/pdf/apple/lisa/hardware/050-4027-A_Parallel.pdf and I don't see anything too obvious, both seem to have very similar circuits, I see PB7 and the gate it goes to are above the VIA in one drawing and below in the other, but they're the same circuit. Both have resistor packs. Both have the LS280, 245, 09 on PA lines for the parity checker, both use the phi2 clock, they do share the DTACK circuitry... so what else could it be?
Does it work on both ports if you're not booting from it? i.e. just as a data disk?
I started a disassembly of the 2x parallel ROM here: https://onlinedisassembler.com/odaweb/c2Cu8Ejq/0 I removed the 1st 5 words from the disassembly, but not sure if that's correct or not. The ROM is here: http://bitsavers.org/bits/Apple/Lisa/firmware/341-0193-A.BIN
Not sure what the offsets are supposed to be as it's a bit weird. The 1st 5 words are: e0 02, 03 fd, 60 08, 60 02, 05 c7
e0 02 - this is the card ID, e0=has icon, has status, is bootable. 02=2x parallel port card id
--- Code: ---03fd - number of words in the ROM
6008 - this is the offset to the status entry routine
6002 - this is the boot routine
05c7 - icon pointer in packbits format.
--- End code ---
But 6002 is outside the size for this card, so it's got to be at 20002 most likely, not sure what the significance of the 60 is.
The first instruction is a branch to 202a2 which checks d0 for the device id and makes decisions from there, likely loading the address of the VIAs and the device to boot from.
stepleton:
Thanks for looking at the ROM! Now I know from my Applenet disassembly that 6008 and 6002 aren't sizes: they're the first words of the status entry and boot routines themselves. Of course there's not much room for code in 16 bits each: you just get one small instruction. So the one instruction in both cases is: jump to the place where the real code is.
--- Quote ---Does it work on both ports if you're not booting from it? i.e. just as a data disk?
--- End quote ---
It does work as a data disk, which was one of the things that was such a mystery. But thanks to the probing I did just now, I have an answer for why booting alone was a problem. I wonder if I would have figured it out from a disassembly.
For some reason the Lisa parallel port card likes to give the ~PCMD (that's the "HEY HARD DRIVE" signal for folks following along) on both of its ports a good shaking prior to talking to either of the ports on boot: both ports get the business no matter which port you're booting from. I don't know the reason for this, but it also seems to happen during the POST, which must mean that it's happening in the status entry routine. (IIRC, in addition to during POST, the boot ROM runs the status entry routine prior to running the boot routine.)
Now, when Cameo/Aphid is on the lower port, it's no problem: see the first attachment.
The blue trace is ~PBSY, the "We are dealing with your request" line that comes back from the hard drive. Basically, the Lisa stabs ~PCMD down very briefly, then gently pulses it down a couple of times more. This three-wiggle manouvre repeats eight times for some reason.
(The reason ~PCMD doesn't drop to 0, I think, is because I've got a series resistor on the line for termination, and there's a pullup on the Lisa end, so the probe is sitting in the middle of a voltage divider.)
Now let's move Cameo/Aphid to the top port: see the second attachment.
You can see here that our poor guy is a little more confused by all this nonsense: while last time ~PBSY goes high very crisply after a wiggle, now it sometimes takes a little longer. The final wiggle keeps ~PBSY low for nearly 11 seconds, which is way too long for the parallel card boot routine: it times out.
Look at how long it takes ~PBSY to return to high after wiggles 1, 2, and 7. It's very suspicious that the delay seems to be an integer multiple of other obvious intervals --- I'd say it's about 88us given the labeled period there.
My hunch now is that we're not seeing the entire story of the wiggles. There are probably other control lines to check out. I bet we're getting treed up at this point:
https://github.com/stepleton/cameo/blob/master/aphid/firmware/aphd_pru1_control/aphd_pru1_control.cc#L328
waiting on PR/~W, the direction signal from the parallel card. Maybe it's doing something weird.
As you've noted, the upper and lower ports seem pretty similar on the schematic, so any difference between the two may be down to the layout?
http://bitsavers.org/pdf/apple/lisa/pcb_pictures/620-0135-A_Parallel_F.jpg
Those traces for the upper port are longer...
rayarachelian:
So then my guess is that the aphid hardware is a lot faster and notices these ups/down where as a real profile and IDE file use a slower processor which would average them out to a nice flat line. So either a switch debounce circuit would solve this, or you could do something similar via software where you don't act on the CMD going back up to 5V immediately, but wait a bit to see if it gets pulled down again, etc. before flipping BSY?
Edit: This is what I was talking about regarding the Schmitt trigger circuit: https://mansfield-devine.com/speculatrix/2018/04/debouncing-fun-with-schmitt-triggers-and-capacitors/
stepleton:
You may be right about that. The main problem facing any theory though is that it has to account for why there's a problem on the upper parallel port but not the lower one.
I got some traces of PR/~W, which is also wiggling in a confusing way, but there wasn't really much difference there between the two ports that way. The signals seem very similar. It's possible that whatever the problem is, it's being provoked by a different control line.
Can't hold back my "software guy" any longer. To narrow down the possibilities for signals that are triggering the problem, it will help to know what state the Cameo/Aphid state machine is in when it gets stuck for so long. This kind of inspection was a big part of my initial debugging process, which is why the state machine implementation has statements like these:
https://github.com/stepleton/cameo/blob/master/aphid/firmware/aphd_pru1_control/aphd_pru1_control.cc#L318
The heart of the PocketBeagle single-board computer is a TI AM335x SOC, which is an ARM core paired with two real-time I/O processors called PRUs --- they're decent little RISC devices. The PRUs talk to the pins and then the ARM talks to the PRUs. It's handy because if Linux on the ARM wants to steal the CPU away from the disk emulator in order to do some other task, it won't interfere with the timing that the parallel port hard drive protocol requires. Dr. Schaefer notes on his IDEfile page that the Apple can send bytes down the cable (or demand that they flow back up the cable) at a megahertz, and the drive just has to deal with it; there's no flow control like on a serial port, so it can't drop the ball.
Anyway, the state machine code linked above is running on one of the PRUs. It's recording the current state to a shared memory region that's accessible to the ARM, so you can write a nice program for the Linux side that probes that shared memory in /dev/mem and reads that useful debug information. Thank goodness I took notes on where to look:
https://github.com/stepleton/cameo/blob/master/aphid/firmware/aphd_pru1_control/aphd_pru1_shared_memory.h#L95
I used to have such a program, but I seem to have lost it forever. Too bad; I can write another one. Time to remember how to mmap again...
rayarachelian:
shmem ops are pretty straightforward, it's almost like using malloc but it's mapped to a "file", you could use that with /dev/shm, and once you get a pointer back, the offset is equivalent to the file offset.
However, you mentioned something yesterday that might be a clue, you've noted that the upper and lower ports have slightly different lengths in their traces. This shouldn't matter at all because normally you'd have a ProFile at the end of a 3 foot 25-conductor cable, right?
So are you hanging the Aphid directly on the port itself? Or is there a cable between it and the port?
Perhaps hanging it off the port is the issue because the wire is too short and it's causing some kind of EM/RF interference from some other noisy thing in the Lisa, or just the right condition to cause a resonance?
Or perhaps the wires are indeed too short and the resistor pack terminating the pins is now slightly out of spec enough due to changed capacitance? I recall seeing something similar with 10B2 and early 10BT ethernet where if your cable was too short you'd have issues.
In terms of the direction of the BSY line and the voltage converter, you could always skip going through that chip and instead use a resistor to drop the voltage from ~5v to roughly 3.3v if you think it's the converter chip. And if you want to ensure direction, use a diode too, which would also drop the voltage by ~.7v. Hmm, or instead of a resistor, if you'd use 3 diodes in series it could drop the voltage from 5v to 2.9v which likely should still ok with the rest of the circuitry.
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