General Category > Lisa Troubleshooting and Repair

RamStak Issues

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compu_85:
I have 2 RamStak boards, with one populated with the full 2mb installed in my 2/5: One of the RAM slots on the motherboard is bad somehow (any ram installed in that slot makes the system not start). But a RamStack in the working slot with 2mb works great with the Office System (v3.1), Workshop, and UniPlus. That system has H ROMs.

-J

rayarachelian:
Note that I don't know for a fact that it will fail with 150ns or not. In theory it should hold the data line output as long as the OE line is signaled. It's possible that it's the RamStack board that's sensitive to timing, and not the Lisa, or just the Lisa. The only way to find out for sure is once you get the 200ns chips and try it out.

Way it works is that the address lines should be set first from the bus for a read (!AS), then there should be an output enable (!CS - chip select), or optionally also a write signal (!WE + !AS + !CS), and then the bus will wait some reasonable amount of clock cycles for the data (D line output)  from the DRAM chip to be placed on the bus. In the case of the write, the bus will keep the data on the D line for at least that amount of time and it's up to the DRAM to store it properly without dropping it on the floor.

The 150ns/200ns is around what that reasonable turn around time happens to be - either to store, or put the bit on the bus.
There's also the whole refresh mechanism (!RAS)

see: https://www.c64-wiki.com/wiki/RAM the 4164 diagram and http://www.graphics.stanford.edu/courses/cs448a-01-fall/lectures/dram/dram.2up.pdf
The 2nd link shows that timing is a bit flexible.

As it says in the cross-reference section of the wiki, you should in theory be able to use faster DRAM:


--- Code: ---With the help of the cross reference table one can see the classifications of each of the producers for RAM chips. Although they are electrically and mechanically identical, every producer has his own system to mark the RAM chips. While the preceding letters often hint to the producer, the following series of digits indicates the size and organisation of the memory. Next, there are often one or more letters, which most stand for the housing shape. Finally, there is again one or more digits, e.g. "-15", this tells you something about the maximum access speed.

Example: 2114L2 - this memory chip has an access time of 120 ns (nano seconds) and can without any problems be exchanged by a faster chip 2114L1 (100ns), but not by a 2114L3 (150ns) or 2114L4 (200ns). As also today with the PC, you have to not only choose the appropriate memory size, but you also have to know where the limit for the access time is.

For the 4164 DRAM, many C64 has DRAMM-BM-4s marked with 150nS and 200nS speed.

--- End code ---

So while it doesn't work, it should accept 100ns in place of 150ns. But if the board wants 150ns, you absolutely cannot use 200ns.

patrick:
The access time is the minimum time you have to wait after /RAS until valid data is available at the output. It is absolutely not necessary to fetch the data immediately after this time has elapsed, they remain there until /RAS and /CAS have been deselected. 

Of course, not indefinitely, sometime after a few milliseconds the next refresh is due. But a system that is designed for 200 ns access time has no problem with the data being available after 150 or 100 ns. The figures in the data sheet are worst-case values anyway; most chips are faster than specified.

In some cases, there may be problems with the parity check circuit if the access times between individual chips in a bank differ too much. Then the bits arrive one after the other, which can cause glitches if the circuit is not so well designed. To avoid this, all nine chips in a row should have the same speed grade.

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