many different kinds of 256k 30-pin RAM SIMMs (9 chip and 3 chip variety) to troubleshoot the issue
The problem (possibly not the only one, but a major DRAM compatibility issue) is that the Lisa design implements 256 cycles per 4ms of refresh. DRAM chips larger than 256K x1 typically need more (eg. 512 cycles per 8ms), and so are not refreshed adequately. They may appear to work at first but will fail in a few minutes.
A 256K x9 SIMM with 3 chips may be made with one 256K x1 chip (for the parity bit) and two 256K x4 chips. The 256k x4 chips probably (maybe always, IDK) require more than 256 cycles of refresh. I speculate that an over-performing part may still work if it hosts the video page.
A modification was in the works to convert the SR design to "hidden" refresh to support most DRAM chips, but since 30 pin SIMMs of any size (and sockets) are no longer inexpensive, we really need a new memory board design that uses current RAM chips.
TLDR: Check the DRAM chip's datasheet: if it specifies more than 256 cycles of refresh, it probably won't work in the SR board.