General Category > Lisa Troubleshooting and Repair

BLU and Priam Datatower puzzlement

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sigma7:

--- Quote from: Al Kossow on June 10, 2024, 08:51:44 pm ---i'm not sure if BLU has code in it to spin up the priam

--- End quote ---

When the Priam is selected as the object of any hard disk command (eg. identify device, read from, write to, etc.), BLU first attempts to verify there is actually a Priam there by sending it these commands:

$07 - Software Reset
$82 - Sequence Up & Wait
$08 - Set Logical Sector Mode

Not getting past the Software Reset command will prevent it spinning up. This would (probably) be the case if the controller has a self-test failure.

Edit: Selecting Logical Sector Mode is command $08 with parameter $40, not command $40

sigma7:

--- Quote from: Al Kossow on June 10, 2024, 08:51:44 pm ---i've been staring at the logic traces and i think the data bits ended up scrambled somehow

--- End quote ---

I suggest connecting the logic analyzer to the DS101 itself for testing that all the circuitry before it has the bits connected correctly (perhaps you've already done so); then use service mode to poke the individual bits to confirm they are correctly connected and unique.

Since the protocol is so simple, you can also send basic commands and read responses interactively using service mode. (Although commands that involve data transfer would be more practically done by calling a routine.)

Al Kossow:
Do you have much experience debugging the DS101 board?
I've been off building a 40 pin cable tap for the analyzer, got it working last night and it does show the bits in
the right order. I also wired up two of the signals that aren't brought across, one is supposed to show if it passed
its self-test if i'm reading the docs correctly.

I am going to try poking at a SMART-E board with an arduino bolted onto the cable tap next, since I do have schematics for that, and it uses an 8085 and is a much simpler board. It uses the same interface protocol. That way I can follow everything that happens on the SMART-E after assertion of RST/

One thing I haven't tried yet is looking at the SMART-E board attached to the Lisa interface to see how it behaves

Will the DS101 pass self-test if no drive is connected?

sigma7:

--- Quote from: Al Kossow on June 15, 2024, 03:06:14 pm ---Do you have much experience debugging the DS101 board?

--- End quote ---

Not really. My only 'successful' efforts were the two boards that failed their self test that I've mentioned by email previously. The one with the invalid DRAM write timing (where the write signal was held after the address lines changed at the end of the cycle, causing erroneous writes to semi-random addresses -- "fixed" by adding some logic to terminate the write signal sooner), and the one isolated to a non-functional data bit in the DMA controller, which remains unrepaired in that state.

Since that effort some years ago, I have received a couple of more DS101s from eBay (Many thanks to James Denton), but when I've tried to test them, I find my Priam DataTower no longer works (drive spins up, seeks, and a data stream is present from the head amplifiers, but an ambiguous error occurs -- I presume the drive's digital section is the problem as the symptoms are the same with multiple controllers).


--- Quote ---I am going to try poking at a SMART-E board

--- End quote ---

I suspect the DS101 variety of controller is only needed to access the QIC Tape.


--- Quote ---Will the DS101 pass self-test if no drive is connected?

--- End quote ---

I think so... I'll see if I can try it.

Al Kossow:
there is something wonky going on with the interface.
I put up some jpgs of traces in http://bitsavers.org/projects/datatower/traces
The boot is really strange I tried booting twice and there are two reads of the status register
a second before it does then it does a two byte write of 00 then 07
Looking at the smart-e schematic, it flags if there is a back to back command write

The BLU commands make a little more sense

the cmd 7 in ident is failing with a ram failure ?

wr 2 0
wr 4 0
wr 6 0  <--- this would make sense if the params are written to the word-write adr. I wonder if the byte/wrd adr is flipped on the interface just for writes?

wr 0 0 ???
wr 0 7

rd adr 2 -- completion code 1a
rd adr 3 is 0
then it reads 2 and 3 again ??



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