Good news, I think I fixed it!
It turns out that most of my confusion last night was stemming from me misreading the logic analyzer trace. A few dozen milliseconds after the successful read of block 0, there was a small blip on one of the ProFile signals, but I wasn't paying full attention and thought that it was noise on PD7. Nope, it turns out that it was actually /CMD (right below PD7 in my trace), and it was of course the boot ROM's attempt at reading the next block, block 1.
But for some reason, ESProFile wasn't responding by asserting /BSY when the Lisa asserted /CMD. And given the really short timeout period of the C ROM, the Lisa gave up before ESProFile had time to respond, whereas it waits long enough to get a reply in all the later ROMs.
Why wasn't it responding though? Well it turns out that it was related to interrupts, just as I had guessed earlier. The way that the code previously worked is that it would disable interrupts during the time-sensitive parts of the ProFile operation (the parts where /STRB is being pulsed) and would re-enable them afterwards. But the re-enabling would sometimes cause the code to go service interrupts for several milliseconds since several had queued up while they had been disabled, primarily generated by FreeRTOS. And when the Lisa lowered /CMD to read block 1, we were still off servicing interrupts and didn't see it until it was too late and the ROM had already timed out.
After reviewing the code, I realized that I wasn't actually doing anything that used interrupts, so I could safely get away with permanently disabling them instead of only disabling them during the time-critical parts. I had already turned off the interrupt watchdog timer by directly writing to some ESP32 config register a while back, so the ESP32 wouldn't notice it and get mad at me. And sure enough, that did it!
The error 85 that you would sometimes get was thanks to a minor bug with handling /PRES that only appeared with the comms sequence of the C ROM, which I've also fixed now.
I've attached the fixed firmware here, so I'd appreciate it if @reid (or anyone else with a C-ROM Lisa 1) would try it before I put it up on GitHub. I've tested it with a bunch of OS's on a 2/5 with the H ROMs put back in to make sure it didn't break anything there, but it still needs to be tested with the XLerator to make sure everything still works there as well. I don't have my XLerators handy right now, so I'd appreciate it if someone with an XLerator installed could test it booting XLerated MW+ or MW+][ as well!