LisaList2

When I have a moment, I'll take the time to sit down with a schematic and learn something.

The schematic linked in the vcfed post is an older version (E), whereas the final version is J: Lisa Video Board Rev J Schematic.

An interesting and technically detailed discussion around fixing a video board ...

Thanks for the tip!

Hugo mentions some designs having a variable inductor as a coarse width adjustment...

The earlier versions of the video board included the variable inductor L3, which was adjustable through the small hole in the back of the card cage area. If you have one of these video boards, you'll find that adjusting L3 doesn't really do anything (at least it didn't seem to have an effect for me; if you do want to try adjusting it, use a non-metallic tool).

L3 was deleted with rev. F

If you ship one of these boards, L3 being tall and weak is prone to breaking loose; if so, you can just remove it.

An interesting and technically detailed discussion around fixing a video board is taking place on vcfed:

https://forum.vcfed.org/index.php?threads/lisa-video-fault.1244688/

When I have a moment, I'll take the time to sit down with a schematic and learn something.

That's so cool; I had no idea that the team signed the last system!

I was reading the List of All Lisa Software thread and its Google Sheet, which subsequently links to a PDF titled "The People Behind the Lisa's Development" from 1997.

In section X.9, the author reserves space for the people who manufactured the Lisa at Apple's Carrollton, Texas facility. He did not know their names when the PDF was made, and his final date of manufacture is off by one year ('85 vs. '84), but he correctly mentions that some of those remaining team members signed the inside of the very last Lisa's top panel. Seems a very Apple-like thing to do 

John Woodall of VintageMicros had mentioned this signed panel to me previously and kindly shared a photo of it. Attached here, with his permission.

Thanks so much ! I also noticed that the +5V line of P6A (pin 20) is open vs. all the other pins. Shouldn't resistance always show some finite numbers (say a few Mohms), like it does for all others pin-to-ground values on that chip? In any events, I did buy a spare one on eBay.

And thanks for the troubleshooting info. Interesting that on the 2/10, they changed the P6A/LS323 chips to a pair of LS85.

I'm off for a trip abroad, so I probably won't report again until after Sept 16. Much appreciate your help again, as always !!

(reserved for future use)

This is a preliminary draft of this topic, there may be some mistakes/errors...


Reviewing the Rev H Boot ROM Listing, error 57 equates to EDISK, with the comment "disk error"; it appears to be limited to floppy disk controller errors.

Searching the code for EDISK, we find it at address $1152 (that's offset $1152 from the start of the ROM, shown as 1152 in the left column of the listing), and at $1186, and at $14C6

So there are 3 possibilities for where this error might be generated/detected.

The ROM version display and the timing of the error message help narrow down which is happening...

1) $1186 -- The I/O ROM version is displayed on the screen by the code at $111A, which writes the "/" character to the screen after the CPU Board ROM version (eg. "H"), then reads the I/O ROM version from the FDC shared RAM, and writes that to the screen. If the attempt to get the I/O ROM version fails with a bus error, execution will redirect to DSKVCT so nothing will be displayed after the "/".

A bus error will occur if the 8T97 at U2F does not assert /DTACK when accessing the shared RAM. See this topic for suggestions for troubleshooting bus errors: Troubleshooting Bus Errors

If /DTACK is generated correctly, but the shared RAM is not working properly, or the FDC did not successfully write its ROM version number into the shared RAM, then the I/O ROM version shown may be incorrect or even random.

If service mode is available, one can test the shared RAM manually via reads and writes to odd addresses from FCC001 to FCC1FF. The end of this range is used for the Lisa Parameter RAM, and the 6504 stack, and the beginning of the range is used for FDC operation (values, commands, etc.) so for random writes, using the middle of the range is least likely to cause any hiccups.

The I/O Board RAM chips are two of the few static sensitive devices on the Lisa circuit boards, so they are among the parts most likely to be found faulty.

2) $1154 -- After displaying the I/O ROM version, the self test checks to see if the FDC has asserted DSKDIAG (U3E-11), which is done after the 6504 successfully goes through its reset sequence. DISKDIAG on the schematic is controlled by the 6504 with writes to the equates BOOTL and BOOTH in the IO_ROM listing. DSKDIAG is set low by /RESET. The 6504 writes to BOOTH (setting DSKDIAG high) when ready to interact with the 68k.

If the FDC is not working, then the state of DSKDIAG will remain low after reset. If the FDC is working or semi-working, then you should be able to see the state of this signal be low upon reset, then go high shortly after. If it is stuck low, then the 6504 circuitry may have some kind of problem.

The Boot ROM Listing suggests the 68k waits 15 seconds for DSKDIAG to go high, so if the amount of time between seeing the I/O ROM version on screen and the error appearing is much less, then the error is likely from $14C6.

3) $14C6 -- After finding that DSKDIAG is high, the 68K:

• checks the startup status from the FDC as stored at $FCC017 is $00 (via code at $1156),
  
• attempts to write $55 and read it back back at $FCC003 in the FDC shared RAM (via code at $1162), and
  
• issues the disable interrupts command to the FDC (via code at $1D46);
  

If any of those fail, error 57 is generated.

The startup status retrieved from $FCC017 will not be $00 if the FDC detected an error upon reset; see error numbers extracted from the I/O ROM listing below (note the pic shows decimal numbers, not hexadecimal as used in Service Mode).

If the keyboard is working, then one could use service mode to do these checks manually to see which one is failing.

eg. enter service mode and type

1fcc017 1<return>   (to read 1 word from FCC017, the status byte where error codes are returned)

2fcc003 55<return>  (to write 1 byte to FCC003, the command byte where commands are issued to the FDC)
1fcc003 1<return>   (to read 1 byte from FCC003)

I noticed that the P6A "PROM State Machine" socketed chip (U4B) is also quite hot. If I remove it, I have activity 100% of the time on the 6504. Could the failure of this chip explain code 57 ? What's the purpose of this chip ?

U4B is a bipolar PROM and will naturally run warm/hot as its power consumption is about 1/2 Watt. The video PROM on the CPU board is the same type (with different programming) so you can compare to its temperature.

P6A is the same PROM as on the common version of the Apple II Disk Controller board. It is used to encode/decode the bitstream to/from the floppy disk drive. The explanation of The Logic State Sequencer in chapter 9 of "Understanding the Apple II" is an explanation of its function (perhaps there is a better one, dunno). This state machine is indicative of the talents of Steve Wozniak... if you find it interesting or even challenging to understand, imagine coming up with it!

The "HardInit" portion of the I/O ROM reset routine will return an error if the state machine doesn't respond appropriately, so I suppose a failure of U4B could cause error 57. See this topic: Troubleshooting self-test Error 57 for a suggestion on checking for this situation.

Yes, the new 8T97 is not getting hot.

And yes, as I described earlier in this thread, the ROM version shows H/9F, and sometimes H/91 (not H/A8). As I was playing around today, I notice that the activity on the data lines of the 6504 is quite erratic. Upon multiple resets, it sometimes shows something, and sometimes not. But in both cases, it still shows error 57.

I noticed that the P6A "PROM State Machine" socketed chip (U4B) is also quite hot. If I remove it, I have activity 100% of the time on the 6504. Could the failure of this chip explain code 57 ? What's the purpose of this chip ?

Oh, and the memory issue I had earlier (gibberish when I had the two 512k boards) solved itself. I put the second board in, and still got gibberish. But after I hit the reset button once, everything was OK. Not too sure what happened though.

Thanks again !