LisaList2

yes thats me, as soon as I get the PS fixed I'll see if there is software on it.

I had five of these made before I found out you couldn't use them as emulators on Apple][ class computers, so I'm just going to keep one for diagnosing my Apple profile drive if anyone's interested in the other four happy to give them to you at cost, you'll have to provide your own ESP32 of course

Good suggestion, but I probably won't add 4MB of RAM because of the extra cost of a second RAM chip. The boards are already rather pricey, and another chip just increases that price further. And plus, I think only a select few people would use 4MB to begin with. I'm guessing that most people who want an FPGA Lisa are probably going to be using it to run the unique LOS/Workshop/Xenix/UniPlus OSes as opposed to your generic Mac OS that can be run (and run better, no less) on any old Mac.

This is a render of a 2MB SUN REMARKETING card. If you look in the center, there's a jumper to convert it to a 4MB card. A mod to the Lisa motherboard is necessary for it to work.

Hi, as the colleague says, the LRambo card was a mod for a Sun Remarketing 2mb RAM card that supported the 4mb option for use only with the Mac system, not with Lisa OS.

Hahaha, you're not kidding; there are a few Lisa Rambos out there.

Thinking he's talking about the LRambo mod as seen here.

I've never heard of a LisaRambo card and Google and DuckDuckGo both just turn up a reality show contestant. What's a LisaRambo card?

Hi, congratulations on the magnificent work done.

I think there's little more to add to the project.

However, if we need to expand the RAM due to parity requirements, we could consider adding 4MB of RAM with the LisaRambo card. This would allow us to enjoy 4MB on a Mac system and switch to 2MB for the Lisa system. But I understand that would complicate the project even further. I'm not sure if it would be possible.

In any case, we are interested in the project once it's completed, for a possible group purchase.

Does anyone have an extra Lisa flyback transformer?

A friend is looking for one.

Thanks!

-J

It turns out that there was one other problem still left with the floppy controller, which was related to clock skew. My addressable latches that drive many of the floppy disk interface signals were being directly clocked off the divided-down 2MHz clock (which is a fabric signal, not a clock net) instead of the dedicated 16MHz I/O clock (with the 2MHz as an enable signal), which was introducing so much clock skew that things would occasionally not work. After fixing that issue by moving over to the 16MHz clock, the floppy controller seems rock-solid!

At this point, I'm trying to test things as thoroughly as possible to eliminate all the bugs that I can find, and I've discovered a couple over the past few days.

One is in LOS 2.0, where the Preferences Window refuses to display the Convenience Settings tab or the Connect Devices tab. Whenever you try to choose either tab, it pops up the "Lisa is having trouble displaying this window, do you want to try and redisplay it" error message. I'm saving this one for later though.

The other two issues occur in LisaTest 2.2. The first of these happens during the VIA test, where LisaTest reports an error code of 7 and a test step of 5. The issue is that nobody has any clue what these codes mean, so I decided to try and throw the VIA test binary into Claude to see if it could help me out. And boy, did it deliver! Go check out my thread on that for all the reverse-engineered info it spat out, but the quick summary is that the error 7 and test step 5 means that it was trying to test Timer 1 of the keyboard VIA and discovered that the timer was running too slow. It loads a value into the timer, tells it to start counting down, and waits for a timer interrupt. Meanwhile, the 68K is incrementing a counter that it's using to time how long it takes to receive the interrupt. Once the interrupt is received, it compares the counter value to an "acceptable" range and if it's within that range then the timer is functioning properly, whereas if it's outside that range then the timer is running too fast or too slow. It repeats this for 22 different timer values. And for timer value 000F, it fails and says that the timer is too slow. The expected counter value here is 2 (range is 1-3, exclusive), but we're getting a 3. I have literally no clue why our timer could be running too slow because the CPU and VIA clocks are scaled together even when the system is overclocked, so it just makes no sense at all. Given that it doesn't fail in LisaTest 3, I'm just going to assume that it's a bug in 2.2 and that the range should be bigger or the bounds should be inclusive or something.

The second LisaTest issue is in the CPU error logic test, which I also reverse-engineered with Claude. It reports an error code of 9 on test step 0x18, which apparently means that the "write wrong parity" test failed and triggered an NMI when it wasn't supposed to. That's to be expected since my parity implementation is only good enough to remember one wrong parity address at a time, whereas LisaTest tests thousands of addresses to confirm that the memory error address latch is working properly. So I patched this check out of LisaTest to make sure that it passes all of the subsequent ones, and guess what? It actually fails another one of them. The one it fails is the very last test, which intentionally triggers a bus error by writing to a nonexistent address and then reads the system status latch to confirm that the BUST (Bus Timeout) flag was properly set to indicate the error. But it's returning with an error code of 35 on test step 0x30, which means that the bus error occurred, but the BUST bit wasn't set in the latch. I'm resynthesizing with debug probes on the bus error circuitry right now; hopefully this will be an easy fix!