> Would be nice if there was some unified standard for all CPU cores...
> well, I suppose MAME/MESS cores would meet that requirement, but I meant
> 68K cores here, so that way multiple cores could be tested together and
> bugs in all of them could be found. I suppose #define is my friend
> here. :-D I could test 3 cores, together, and whenever 2/3 gave the
> same result, the buggy core would be clear - but of course the two
> could be wrong, and the 1 could be right.
>
I've read some people did this work for a new spanish 68k core (can't
remember the exact name but it was related to dreamcast ports of
emulators). In that case the reference was musashi. I think it was
for a MAME port but the goal was speed, not accuracy.
> Testing against a real CPU is the best way to go, but you always need a
> machine with lots of CPU power and network bandwidth. The NeXTStep is
> slow when compared to modern PC's, and the 10BT Ethernet is really a big
> bottleneck for this... the bitfield opcodes which take 3 operands take
> more than a week to run for example and so far produced about 1GB of
> output - only got through most of one opcode so far...
>
This is an interesting approach. Another one would be to get the real
microcode and to emulate it. I've found a good paper for this, but
unfortunatly incomplete. I also found a free 68k hardware
implementation in VHDL. It would be a good start for a "one-chip lisa
project", but it does not support bus errors and all interrupts.
> Well, the good news is in a few months we'll have fixed most of the 68K
> CPU cores out there and what we learn from this can probably be
> reapplied elsewhere.
>
> In terms of the Lisa, ideally, I'd love to have some sort of umbilical
> cord from the Lisa's CPU to a much faster machine that can analyze what
> it does in realtime. I have a logic analyzer which works very well, but
> only for very short runs which is almost exactly what's needed, but it's
> not "deep" enough and can't interface with another machine in real time
> to compare the results. I don't think slowing down the host CPU would
> work too well since I/O would break before anything interesting loads.
> There are modern USB logic analyzers, but I'd need to use them in
> parallel with separate USB PCI cards to get enough bandwidth, and even
> then, it's very tight I/O and requires a very fast set of CPU's to keep
> up...
slowing down the cpu doesn't work for a 68k, due the the NMOS conception. It should work with 68HC000 but I'm not sure the microcode is exactly the same. So only a fast analyzer is a valid option.
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