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[blusnowkitty]

Hey all, does anyone have a RamStack in their Lisa? I bought a bare board a few months ago and only just now got a bunch of 41256Cs to fill it with. Problem is whenever I install the board in my 2/5 in either slot, whether I have it filled with 1.5MB or the full 2MB, and whether or not I'm using an Apple 512k board with the 1.5MB config, the Lisa gives me the beep code for no memory found. The included install pamphlet just says to move W1 to the correct position depending on if you want to use one or two RAM boards, which I've jumpered correctly for single-board and dual-board configs.

Is it also possible that the RAM I bought is simply too fast for the Lisa? I got some 100ns chips, the Apple 4164s are 200ns, and I see a RamStak on eBay right now outfitted with 150ns chips. Other possibilities include that I didn't socket the chips correctly (they appear to be NOS so the legs were still splayed out like they came from the carrier tube and I don't have a fancy leg flattening tool like Adrian Black does), or that the chips were all bad/fake (They all lack the usual remarking signs, but could still be a possibility. I did try the acetone test; the markings on the top did fade a little but it wasn't an instant, immediate black smudge on my Q-Tip. They'll either be originals marked with ink, or they're some very high quality fakes.).

Any thoughts?

[rayarachelian]

Other possibilities include that I didn't socket the chips correctly (they appear to be NOS so the legs were still splayed out like they came from the carrier tube and I don't have a fancy leg flattening tool like Adrian Black does), or that the chips were all bad/fake

Dude! They're like $20, nothing fancy either: https://www.amazon.com/MCM/dp/B00DRDOG2K/

Totally worth it even if you have to do just a few chips. It's a tool you should have. As are those chip puller clips. Saves you tons of aggravation and issues.

I can't speak to the speed issues, but theoretically if the DRAM doesn't leave the data out signal long enough for the Lisa to read it, it will be an issue.
So most likely, you also shouldn't mix different speed chips. It's probably ok if the whole board is the same speed, but not 100% sure. I'd guess @sigmaseven has much info on this than I do.

Since I see a "C" at the end of that chip maybe it's that some are CMOS and the rest are NMOS? I'm just guessing here, but they do have slightly different electrical properties, which might, or might not matter.

(All that said, my experience with PCs is the opposite, and you can use faster DRAM than the machine supports, but still you're also not supposed to mix different types as it causes issues.)

There's also a bug in the Lisa Boot ROM with 2MB, 1.5M works just fine. The 3A ROM works just fine with 2MB, but H and earlier throw a memory error for some reason.

Another test you might try, is to remove all the original chips (carefully and safely static electricity wise) and move the new chips to the top, set the dip switches properly and see if the ROM will pass the test? They should be in gangs of 9, not 8, since the Lisa wants parity memory.

[blusnowkitty]

So most likely, you also shouldn't mix different speed chips. It's probably ok if the whole board is the same speed, but not 100% sure. I'd guess @sigmaseven has much info on this than I do.

Since I see a "C" at the end of that chip maybe it's that some are CMOS and the rest are NMOS? I'm just guessing here, but they do have slightly different electrical properties, which might, or might not matter.

There's also a bug in the Lisa Boot ROM with 2MB, 1.5M works just fine. The 3A ROM works just fine with 2MB, but H and earlier throw a memory error for some reason.

Another test you might try, is to remove all the original chips (carefully and safely static electricity wise) and move the new chips to the top, set the dip switches properly and see if the ROM will pass the test? They should be in gangs of 9, not 8, since the Lisa wants parity memory.

Yeah I am sure mixing speeds is not a good idea but I wanted to just test and see if the RamStak was alive with 1.5. I was not aware of the ROM bug though! I will have to run a solo 1.5 config and see if that changes anything. Do want a nice 2MB Office System config though.

[Lisa2]

Hey all, does anyone have a RamStack in their Lisa? ...
Any thoughts?

I have a couple RamStacks.  According to the manual, you should use 150ns 256K DRAM chips. 
When you said you "bought a bare board" do you mean the board had no RAM installed or it was a blank PCB?
I would try it with just one row populated ( 512K ) first to see if you have RAM issue or a board issue.

BTW, the manual can be found here:  http://www.bitsavers.org/pdf/apple/lisa/macintosh_xl/Dafax_Ramstack_Jul85.pdf

Note that AST did make a 64K DRAM version also, basically a replacement for Apples 512K card.  What are the markings on the board? Can you send a photo?

Rick

[blusnowkitty]

I have a couple RamStacks.  According to the manual, you should use 150ns 256K DRAM chips. 
When you said you "bought a bare board" do you mean the board had no RAM installed or it was a blank PCB?
I would try it with just one row populated ( 512K ) first to see if you have RAM issue or a board issue.

BTW, the manual can be found here:  http://www.bitsavers.org/pdf/apple/lisa/macintosh_xl/Dafax_Ramstack_Jul85.pdf

Note that AST did make a 64K DRAM version also, basically a replacement for Apples 512K card.  What are the markings on the board? Can you send a photo?

Rick

Aha, so that explains things a bit! I did see that manual several months ago before I got my board, and then when I got mine I didn't look closely at that manual cause I thought they would be identical. Turns out, my board started life as a 512k pre-populated configuration and because of that, my manual pretty much only says to set W1 for a solo or dual-board configuration, install the board, and you're good to go. It makes no mention of the RAM timings required or the parity configuration, though I did buy more than enough to fill the board to 2MB. I bet the fact it needs 150ns chips and I got 100ns is the reason why it's not working. You'd think 50ns wouldn't be that big of a deal, but all the stories I've heard of the Lisa being very timing-critical... And by the time I got my board, the original 512k had been stripped off so it was just the logic chips and empty RAM sockets.

For what it's worth, I did try a solo config with 1.5MB, 1.0MB, and 512k of RAM in MEM1 and they all failed. Looks like I need to find some 150ns 41256 chips! Or win that second RamStak on eBay which already has 1.5MB of 150ns chips on it.

And hey, it's not that big of a loss - we learned there's two different manuals for the RamStak and I'll archive the second one, and I now have some memory to upgrade my IBM 5170 (wait, is swearing allowed?) with!

[compu_85]

I have 2 RamStak boards, with one populated with the full 2mb installed in my 2/5: One of the RAM slots on the motherboard is bad somehow (any ram installed in that slot makes the system not start). But a RamStack in the working slot with 2mb works great with the Office System (v3.1), Workshop, and UniPlus. That system has H ROMs.

-J

[rayarachelian]

Note that I don't know for a fact that it will fail with 150ns or not. In theory it should hold the data line output as long as the OE line is signaled. It's possible that it's the RamStack board that's sensitive to timing, and not the Lisa, or just the Lisa. The only way to find out for sure is once you get the 200ns chips and try it out.

Way it works is that the address lines should be set first from the bus for a read (!AS), then there should be an output enable (!CS - chip select), or optionally also a write signal (!WE + !AS + !CS), and then the bus will wait some reasonable amount of clock cycles for the data (D line output)  from the DRAM chip to be placed on the bus. In the case of the write, the bus will keep the data on the D line for at least that amount of time and it's up to the DRAM to store it properly without dropping it on the floor.

The 150ns/200ns is around what that reasonable turn around time happens to be - either to store, or put the bit on the bus.
There's also the whole refresh mechanism (!RAS)

see: https://www.c64-wiki.com/wiki/RAM the 4164 diagram and http://www.graphics.stanford.edu/courses/cs448a-01-fall/lectures/dram/dram.2up.pdf
The 2nd link shows that timing is a bit flexible.

As it says in the cross-reference section of the wiki, you should in theory be able to use faster DRAM:

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With the help of the cross reference table one can see the classifications of each of the producers for RAM chips. Although they are electrically and mechanically identical, every producer has his own system to mark the RAM chips. While the preceding letters often hint to the producer, the following series of digits indicates the size and organisation of the memory. Next, there are often one or more letters, which most stand for the housing shape. Finally, there is again one or more digits, e.g. "-15", this tells you something about the maximum access speed.

Example: 2114L2 - this memory chip has an access time of 120 ns (nano seconds) and can without any problems be exchanged by a faster chip 2114L1 (100ns), but not by a 2114L3 (150ns) or 2114L4 (200ns). As also today with the PC, you have to not only choose the appropriate memory size, but you also have to know where the limit for the access time is.

For the 4164 DRAM, many C64 has DRAMM-BM-4s marked with 150nS and 200nS speed.

So while it doesn't work, it should accept 100ns in place of 150ns. But if the board wants 150ns, you absolutely cannot use 200ns.

[patrick]

The access time is the minimum time you have to wait after /RAS until valid data is available at the output. It is absolutely not necessary to fetch the data immediately after this time has elapsed, they remain there until /RAS and /CAS have been deselected. 

Of course, not indefinitely, sometime after a few milliseconds the next refresh is due. But a system that is designed for 200 ns access time has no problem with the data being available after 150 or 100 ns. The figures in the data sheet are worst-case values anyway; most chips are faster than specified.

In some cases, there may be problems with the parity check circuit if the access times between individual chips in a bank differ too much. Then the bits arrive one after the other, which can cause glitches if the circuit is not so well designed. To avoid this, all nine chips in a row should have the same speed grade.