Re: xenix install problems

From: gilles <gilles.fetis_at_email.domain.hidden>
Date: Thu, 12 Jul 2007 14:15:53 -0700

On 12 juil, 17:21, Ray Arachelian <r..._at_email.domain.hidden> wrote:
> gilles wrote:
> > I found the problem.
> > Xenix uses T1 and T2 timers to generate interrupts.
> > If T1 elapse and T2 elapse when T1 interrupt is served, the interrupt
> > vector does not clear the T2 bit in the IFR register.
> > Interrupts are broken after that event.
> > The VIA emulation is ok, so the problem is probably in the 68k core
> > that should relaunch the IRQ since the line remains set.
> Yeah, so that should cause T2 to generate a 2nd interrupt as soon as the
> mask is dropped back down after the RTE.

I'm not sure RTE is really an active opcode for interrupts on a 68k. I know many emulators uses this opcode to detect the end of an IRQ but it may be a hack. The check for IRQ relaunch should be made when SR is modified (that may happen in RTE, but also in MOVE_SR)

> I'd trace that code and see what happens there. Xenix does indeed to
> strange things on a Lisa.
> What I have in LisaEm is a routine that checks each device to see if it
> wants to fire an IRQ, then see the highest ones matches the mask in the
> status register, and then decide to fire or not. That's what a 68000 does.
> The hardware itself has commands to clear the interrupts, so the
> interrupt service routine in xenix should clear the IRQ. I'm not 100%
> sure as to what the behavior of the via is off the top of my head, you'd
> have to check to see if it will ignore the T2 interrupt if you've
> already handled the T1. I think, but am not 100% sure, that it should
> still trigger another interrupt.
T1 and T2 are wired to the same IRQ line, in the VIA. You need to
access VIA registers to clear the flag and then to clear the IRQ line. In that case, the VIA IRQ line will remain. It may be simpler to relanch the IRQ in the VIA code, but it's wrong to a strict electronic point of view.
For now, I suspect a bug in the 68k core. I don't think all IRQ should be auto-acknoleged.

> I think the way it works is that if the bits are enabled in IER, when
> you handle it, it clears just the bit corresponding to the one that was
> handled in IFR, and then gets to fire again, but check the via manuals
> to be sure.

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