Re: xenix install problems

From: Ray Arachelian <ray_at_email.domain.hidden>
Date: Thu, 12 Jul 2007 11:21:53 -0400

gilles wrote:
> I found the problem.
> Xenix uses T1 and T2 timers to generate interrupts.
> If T1 elapse and T2 elapse when T1 interrupt is served, the interrupt
> vector does not clear the T2 bit in the IFR register.
> Interrupts are broken after that event.
> The VIA emulation is ok, so the problem is probably in the 68k core
> that should relaunch the IRQ since the line remains set.

Yeah, so that should cause T2 to generate a 2nd interrupt as soon as the mask is dropped back down after the RTE. I'd trace that code and see what happens there. Xenix does indeed to strange things on a Lisa.

What I have in LisaEm is a routine that checks each device to see if it wants to fire an IRQ, then see the highest ones matches the mask in the status register, and then decide to fire or not. That's what a 68000 does.

The hardware itself has commands to clear the interrupts, so the interrupt service routine in xenix should clear the IRQ. I'm not 100% sure as to what the behavior of the via is off the top of my head, you'd have to check to see if it will ignore the T2 interrupt if you've already handled the T1. I think, but am not 100% sure, that it should still trigger another interrupt.

I think the way it works is that if the bits are enabled in IER, when you handle it, it clears just the bit corresponding to the one that was handled in IFR, and then gets to fire again, but check the via manuals to be sure. Received on 2007-07-12 11:21:54

This archive was generated by hypermail 2.4.0 : 2020-01-13 12:15:14 EST