Re: OT: 68K core emulation (was Re: LisaEm 1.0.0-RC2 Available for download)

From: Ray Arachelian <ray_at_email.domain.hidden>
Date: Thu, 12 Jul 2007 10:02:31 -0400

gilles wrote:
> slowing down the cpu doesn't work for a 68k, due the the NMOS
> conception. It should work with 68HC000 but I'm not sure the microcode
> is exactly the same. So only a fast analyzer is a valid option.

That's not true.

The Lisa uses an 8MHz 68000, but clocks it at 5MHz due to memory bus sharing limitations, so it's certainly possible to slow down the CPU. Slowing it down further is probably possible as long as the DRAM refresh is not disturbed, and the I/O is allowed to continue, but this is difficult to get right and still be able to run an OS that you can trace through and not worth the effort just to connect an umbilical cord to another machine. :-)

 From the Lisa Hardware Guide 1983, page 4-3:

> 4.1.1 CPU Access to Memory
> CPU and video memory cycles are interleaved on the memory bus. Every
> memory cycle takes 400ns.
> A video cycle occurs every 800 ns; a CPU cycle can occur between any
> two view (video) cycles.

> 4.3.1 Clock Generation
> Timing generation is shown on sheet 2. At B-4, crystal Y1 and its
> associated oscilator
> circuit are used to generate the DOTCK and CK signals. These both
> have a period of 50ns and
> have the waveform shown on figure 4-12.
> ...
> The QB output has a period of 200ns. It is used as the 68000 clock
> and also generates
> the main clock CPUCK, which is distributed through the Lisa.

Also, if you look at the Lisa CPU schematics, on page 2, you'll see a 20MHz crystal Y1- a multiple of 5, not of 8 which is divided down via two gates at U1E and the LS169 4-bit synchronous counter at U1C which breaks it down into the !T0-!T7 clock signals. A 200ns clock period is 5MHz, not 8Mhz. Received on 2007-07-12 10:02:33

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