Re: Troubleshooting X/Lisa RAM boards - second draft

The CPU can force bad parity to trigger the parity error circuit on the memory board to test it.

However, I expect that it doesn't leave bad bytes here and there, so storing the 9th bit may be unnecessary to satisfy the self-test; eg. it may be sufficient to store the bad parity state until the next memory read cycle. That could simplify the memory board substantially.

Another option is to modify the ROM so it doesn't care about the parity test.

>Can the system force bad parity?
>
>I was thinking it should be possible to build a simple 2m board with
>static X8 RAM and a
>74280 parity generator if the system never checked the parity bits
>independently.

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